MT70003 vlsi components for arinc 429 data transmission systems 1 single channel arinc decoder 16/24 bit parallel interface automatic address recognition option on 8/10 bits single 5v supply with low power consumption < 50mw full mil operating range built in parity and word length error detection high/low speed programmable
MT70003 vlsi components for arinc 429 data transmission systems 2 maximum ratings (above which the useful life may be impaired) storage temperature - 65oc to +150oc temperature (ambient) under bias - 55oc to +125oc supply voltage vdd -0.3v to + 7v dc input voltage -0.3 to vdd +0.3v output current (single o/p) 10ma output current (total o/p) 20ma electrical characteristics over operating range parameter description test conditions min typ max units ioh output high current voh=2.8v vdd= 4.5v 1.0 ma iol output low current vol=0.4v 3.2 ma vih input high voltage 2.4 vcc volts vil input low voltage -0.3 0.8 volts iil input load current vss 0.45 ma ioz output leakage current 0.4v < vo < vcc output disabled -40 40 ua ci input capacitance test frequency = 1.0 mhz 2 2.6 pf ci/o i/o capacitance 7 9 pf icc supply current vcc = max. all inputs high, all outputs open . 1.5 ma switching characteristics note unless otherwise stated output loading assumes 50 pf capacitive plus static current within the limits of ioh min and iol max parameter description min max units tri & tfi thi tlo tlo tro; tfo input rise and fall times clock ? period clock ? hi time not reset lo time not reset data ready lo time output rise and fall times 0.9 0.45 200 100 50 1.0 0.55 200 ns us us ns ns ns taz taz output tristates delays relative to changes on not tag en or not data enable. tristate off from not enable - tristate on from not enable (includes worst case output edge time). 300 500 ns ns tplh tlo data ready from not reset data ready . data ready - from data ready . 16 bit bus option; data access incomplete; not data enable lo; lo pulse on not reset data ready < ) +0.05 2 -0.1 2 +0.2 2 +0.1 2 +0.2 us us
MT70003 vlsi components for arinc 429 data transmission systems 3 tplh data ready - from reset data ready - us tplh tplh tplh tplh (16 bit bus option; data access incomplete; not data enable lo; lo pulse on not reset data ready >2 ) data ready - from tag valid (not data enable lo; sequence operation) data ready - from not data enable (tag valid hi; not reset data ready hi) data ready from not data enable - tag valid from not reset data ready - (data access completed) us us us us address recognition times address recognised settling time from tag valid) (external recognition mode select hi) ) tag inputs settling time from tag valid (internal ) recognition mode select lo) ) address recognised end of hold time from tag ) valid ) tag inputs end of hold time from tag valid 6 4 -0.3 us us general this circuit receives serial data from a buffered arinc 429 bus into a 32 bit shift register. at the end of transmission the received word is checked. it is only considered to be ?good? if the overall parity is odd and the length is 32 bits. if the word fails these checks a transmission fault flag is set. if the word is ?good? the tag bits are loaded into a tag latch and a tag valid flag is set. either internal or external address recognition can be selected according to the state of mode select. if the address is recognised within 4 us time window a 32 bit word latch is updated from the shift register. thus the word latch only contains a ?good? word whose address has been recognised. the contents of the word latch can be accessed whenever data ready flag is hi. it is available on a parallel trio-state output highway which is either 16 or 24 bits wide according to the state of 16/24 bus select. in the former, the 32 bit word is output in 2 halves and the state of output datamux indicates which half is present. in the latter case bits 1 to 8 (the tag bits) are not available but the remaining 24 bits are presented together. the user signals his receipt of the arinc word by pulsing not reset data ready low indicating that data access is complete which cancels tag valid and data ready. the user has a whole word transmission time to access the word latch without entering an overrun condition. when ?end of word? is detected an internal sequencer is initiated. firstly, tag valid is examined. if this is still hi an overrun flag is set. next the data access logic is initialized and both tag valid and transmission fault are cancelled. once set, the overrun flag is only cancelled by a ?data access complete? signal. thus the presence of an overrun flag signals that the rate of servicing the word latch is slower than the transmission rate. note that data ready and data mux always refer to the status of the output data available from the word latch which cannot be updated unless the user requests it, whereas tag valid and transmission fault always refer the the latest received word. the tag latch is always updated when tag valid is set but unless this tag is recognised the contents of the trag latch will bear no relationship to the contents of the word latch.
MT70003 vlsi components for arinc 429 data transmission systems 4 arinc 429 word structure an arinc 429 word is 32 bits long. the first part of the word to be transmitted is the lable (tag) of which bit 1 is the most significant and bit 8 the least significant. bits 9 and 10 are reserved for the source/destination identifier in some formats otherwise they are used as data pad bits. when circuit input identifier is wired hi bits 9 & 10 are treated as extra tag bits and contribute to address recognition but when identifier is wired lo bits 9 & 10 are excluded from address recognition. bits 11 to 29 are the data field of which bit 11 is the least significant, bits 30 and 31 are reserved for the sign/status matrix and bit 32 is the parity bit. m for high speed operation the bit rate must be 100 kilobits per second + 1% and circuit input fast/slow select must be wired lo. for low speed operation the bit rate must be in the range 12.0 to 14.5 kilobits per second and the selected rate should be maintained within 1%. fast/slow select must then be wired hi. internal timing this is determined by a 1 mhz clock applied to ? in. this clock is asynchronous with the bit rate and should be maintained within + 10%. word synchronisation the digital word is synchronised by reference to a gap of 4 bit times (minimum) between words. the beginning of the first transmitted bit following the gap signifies the beginning of the next word. spike rejection (timing asumes clock period = 1 m s) the circuit incorporates pulse rejection filters on both inputs. this will reject pulses less than 2 m s duration and accept pulses greater than 3 m s duration. internal address recognition if mode select is wired lo internal address recognition is performed during the sequencer period. during the sequencer period. if identifier is lo the states input on t1 to t8 are internally compared with bits 1 to 8 of the tag latch and only if they are equivalent within 4 m s of tag valid being set is the address recognised. although the states on t9 and t10 are ignored, these inputs should be held at good logic levels otherwise the circuit supply current could increase. if identifier is hi then t9 and t10 are also compared against 9 & 10 of the tag latch. with mode select held lo the conditions on input pins address recognised and tag enable are ignored. since these pins have internal pull-up transistors they need not be connected if not required. external address recognition (timing assumes clock period = 1 m s ) if mode select is wired hi the internal address comparator is inhibited. t1 to t10 respond as tri-state output ports enabled whenever nottag enable is lo. then the contents of the tag latch are presented to the tag output bus. the normal sequence of operations in this mode is for tag valid to be set at the end of a good word. the user takes this as a singla to interrogate the tag latch by enabling the tristates. within 4 m s of tag valid going hi a decision is taken whether or not to load the word latch via address recognised.
MT70003 vlsi components for arinc 429 data transmission systems 5 if either mode of operation is an address recognition signal is not detected within 4 m s of tag valid being set this flag is automatically cancelled and the word latch is not updated. conversely, if an address recognition signal is detected within 4 m s of tag valid being set and is held for at least until 6 m s after the rising edge of tag valid then the word latch is updated. tag valid then stays hi until cancelled either by data access complete or the detection of the end of the next received word. data bus the contents of the word latch is output onto a data bus enabled by a lo on not data enable. the status of the output bus is indicated by data ready. this flag is automatically held lo whenever data enable ia hi. data ready is held lo for the duration of the internal sequence, whilst not reset data ready is held lo and whilst data mux and the output date are settling. otherwise data ready is set soon after the word latch has been updated and cancelled when data access is complete. 24 bit option for the 24 bit format 16/24 bus select is wired lo. data mux is always hi to indicate that bits 17 to 32 are output on d1/17 and d16/ 32 respectively and in addition bits 9 to 16 are output on d9 to d16. data access is complete when the user pulses not reset data ready with a single lo pulse of width greater than 100 ns. 16 bit option 16/24 bus select is wired hi. data mux is reset by the sequencer at the end of word. when data ready is set, bits 1 to 16 are available on d1/17 to d1/32 respectively. the user signals acceptance of the first half by pulsing not reset data ready lo. then data ready cancels whilst data mux and data ready has been taken hi, data ready re-appears. data mux is now hi and bits 17 to 32 available on d1/17 to d16/32. data access is complete when not reset data ready is pulsed lo for a second time. end of word detection this is detected by a gap counter which times out whilst ?o? detect and ?1? detect are lo for a time equivalent to 2 2 bit periods. having timed out it generates an end of word signal which sets overrun if tag valid is still hi and triggers the control sequencer. bit counter this counts the number of shift pulses applied to the shift register. it is not allowed to count past state 33 and is reset by the control sequencer. for a good word to be detected it must be in state 32 at the end of the word. parity checker this is reset along with the bit counter. it toggles whenever a logic ?1? is shifted into the register. for a good word to be detected it must be in a hi state at the end of the word. circuit initialisation the circuit can be initialised at any time by holding not reset lo. this pin has an internal pull-up transistor. all the flags are immediately cleared and the circuit is locked whilst not reset is lo. the minimum duration of lo is 200 ns. the removal of the reset condition occurs on a rising edge of ? in following not reset going hi. applications instrument displays
MT70003 vlsi components for arinc 429 data transmission systems 6 it is anticipated that the 24 bit data bus option will be required and that the data tri-states will be permanently enabled by wiring not data enable lo. if only one specific label is of interest this can be hard wired onto the tag ports conditioned as inputs by wiring mode select lo. then internal address recognition will be performed. if a range of labels is of interest then mode select can be wired hi. the tag ports are then conditioned as outputs. by wiring not tag enable lo and by using some simple external ?acceptable label? decode to drive address recognised only the required transmissions are loaded. note that in this mode if address recognised is not connected then every good transmission is loaded into the word latch irrespective of its label since this input has an ?on chip? pull-up transistor. several of the pins may not be of interest e.g. overrun, transmission fault, tag valid, data ready, not reset data ready, data mux, in which case they need not be connected. this will not impair the basic function since a good, recognised transmission will be maintained in the word latch until overwritten by the next good, recognised transmission. general processor systems it is anticipated that the 16 bit data highway option will be required. many users will wire mode select hi and employ a label identification p.r.o.m. to generate the address recognition signal. a direct memory access can be performed to transfer wanted data from the word latch into memory. if the user requires an indication of the word transmission rate he can externally ?or? transmission fault with tag valid. the rising edge of such a waveform could be used to trigger a timer.
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